The Universal Verification Methodology  (UVM) is a complete methodology that codifies the best practices for efficient and exhaustive verification. One of the key principles of UVM is to develop and leverage reuasable verification components - also called UVM Verification Components (UVCs). The UVM is targeted to veriy both small designs and large IP-based system-on-chip (SoC) designs.

The UVM has all of the verification features and capabilities your management might ask for to justify its use.

• It is mature
• It is open
• It is compatible and portable

On the technical side, the UVM delivers a common, objected-oriented, UVM verification component (UVC) use model and unsures that all UVM-compliant UVCs will interoperate, regardless of origin or language implementation. Key features of the UVM include:

• Data design
• Stimulus Generation
• Building and Running the Testbench
• Coverage Model Deisgn and Checking Strategies
• Built-in Analysis and Debug capabilities
• User example